This invention relates generally to the art of electronic or fluid flow signal apparatus, and more particularly to the art of analog-to-digital converters.
An analog signal may be described as one that varies as a continuous function of time and is capable of assuming an infinite number of values, usually between an upper and lower limit. A digital signal, on the other hand, must conform to more rigid standards. A digital signal must assume the guise of either a "high" or a "low" signal, often referred to as a "1" or a "0", respectively. These "highs" and "lows" may be used to perform a variety of mathematical functions within the binary number system; such capability forming the backbone of the modern digital computer.
Unfortunately, while digital signals are uniquely suited for use with such computers, most signals as they are found in actual operating systems are of the analog variety. Since such analog systems are inherently unsuitable for use with digital systems, a need arose to make the two compatible. The answer was to convert the analog signal into a digital counterpart. That is, a given analog signal would be subdivided into a number of smaller parts, and each part would be ascribed a binary number assignment. In this way any analog signal could be approximated as a binary number, the number being represented by a digital signal suitable for digital arithmetic calculations. Needless to say, the larger the number of subdivisions and the smaller the part was with respect to the largest possible analog signal, the greater the accuracy of the digital approximations as represented by a concurrently larger number of bits, or parts, as described above.
A number of analog-to-digital converters are well known in the prior art. One in particular utilizes a string of comparator units, each having a successively smaller reference signal, such that the input analog signal may be particularized by the various selected thresholds. One great advantage of this system is its relatively high operating speed. Unfortunately, this technique must usually be limited to only a small number of digital bits due to the many comparators required. This problem has been specifically defined in a handbook entitled Data Conversion Handbook, copyright 1974, by Donald B. Buck of Hybrid Systems Corporation. In particular, at page 3-3 of the above identified handbook, the author notes, "because this technique requires a comparator for each state or level, 2.sup.n -1 comparators are needed to digitize to n-bit resolution and, hence, the number of comparators quickly becomes prohibitive from a cost and size point of view. An 8-bit encoding, for example, would necessitate (2.sup.8 =256) 255 comparators. Further, due to realities such as ground loops, input loading, etc., the tendency to oscillate also restricts the maximum number of comparators, hence bits of resolution, which are feasible to use. While 4 bits (15 comparators) in 20-50 nano seconds is fairly easily achieved, 7 bits (127 comparators) would be an ambitious, and perhaps suicidal task."
Other lower speed ways of performing an analog-to-digital conversion include the ramp staircase method, the successive approximation method, the single-slope integrating method, the dual-slope integrating method and the voltage-to-pulse rate method. Other methods and apparatus may be found at U.S. Pat. No. 3,638,218 to Kaneko et al and U.S. Pat. No. 3,641,562 to Hlotorda.
The competing interests are easily discernible from the above. On the other hand, accuracy and speed are coveted, for these are parameters and capabilities a digital computer is inherently well qualified to exploit. On the other hand, physical reduction to practice must include some finite number of elements, which may not be compatible with the desired accuracy. What is more, under the prior art systems, accuracy of even a moderate degree is obtained at the great sacrifice of speed.